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Quad, IEEE 802.3at/af PSE Controller
for Power-over-Ethernet
Power Status Register (R10h)
The Power Status register (R10h, Table 16) records
the current status of port power. On power-up or after
a reset condition, the port is initially unpowered and
the Power Status register is set to its default value of
00h. PGOOD_ (R10h[7:4]) is set to 1 at the end of the
power-up startup period if V OUT_ - V EE > PG TH for more
than t PGOOD . PGOOD_ is a real-time bit and is reset to
0 whenever V OUT_ - V EE P PG TH , or a fault condition
occurs. PWR_EN_ (R10h[3:0]) is set to 1 when the port
power is turned on. PWR_EN resets to 0 as soon as the
port turns off. Any transition of PGOOD_ and PWR_EN_
bits set the corresponding bit in the Power Event register
(R02h/R03h, Table 8).
Pin Status Register (R11h)
The Pin Status register (R11h, Table 17) records the state
of the A3, A2, A1, A0, and AUTO pins. The states of A3
and A2 (into ID[1:0]), A1 and A0 (into SLAVE[1:0]), and
AUTO are latched into their corresponding bits after a
power-up or reset condition clears. Therefore, the default
state of the Pin Status register depends on those inputs
(00XX–XX0X). Changes to those inputs during normal
operation are ignored and do not change the register
contents. A3, A2, A1, and A0 all have internal pullups,
and when left unconnected result in a default address of
0101111 (2Fh). Connect one or more low before a power-
up or device reset to reprogram the slave address.
SLAVE[1:0] also typically indicates which of the 16
PSE-ICM ports the slave device controls (Table 18).
Table 16. Power Status Register
ADDRESS = 10h
SYMBOL BIT NO.
TYPE
DESCRIPTION
PGOOD4
PGOOD3
PGOOD2
PGOOD1
PWR_EN4
PWR_EN3
PWR_EN2
PWR_EN1
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
Power-good condition on port 4
Power-good condition on port 3
Power-good condition on port 2
Power-good condition on port 1
Power is enabled on port 4
Power is enabled on port 3
Power is enabled on port 2
Power is enabled on port 1
Table 17. Pin Status Register
ADDRESS = 11h
SYMBOL BIT NO.
TYPE
DESCRIPTION
Reserved
Reserved
SLAVE[1:0]
ID[1:0]
Reserved
AUTO
7
6
5
4
3
2
1
0
—
—
R
R
R
R
—
R
Reserved
Reserved
Slave input (A1 and A0) latched-in status (Table 3)
ID input (A3 and A2) latched-in status (Table 3)
Reserved
AUTO input latched-in status
Table 18. PSE-ICM Port Control Mapping
SLAVE[1:0]
00
01
10
11
PSE-ICM PORTS CONTROLLED
Slave device controls ports A, B, C, and D
Slave device controls ports E, F, G, and H
Slave device controls ports I, J, K, and L
Slave device controls ports M, N, O, and P
35
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